1  The Goal of This Experiment

By using an FPGA, you can build the circuit without soldering and each pair of students can use the same module. This technique will be valuable, later in research or any enterprise, since you can quickly make moderately complex circuits and yet quickly make changes as the needs change.

2  Xilinx FPGA Introduction

A Field Programmable Gate Array, commonly known as an FPGA, is a general purpose programmable IC which is mainly used in the digital design environment that requires flexibility in design and fast turn around time.

In contrast to design using commercial ICs, FPGA can be configured to the designer's specific circuits in a single chip. In addition, in the case of design errors, FPGA can be redesigned and reconfigured easily in software, where as in the commercial IC design, it is not so easy to modify the already connected circuitry. In comparison to EPLD (Electrically Programmable Logic Device), FPGAS have more levels of registers and a more general routing topology. This renders the EPLD less useful in more general systems, especially in pipelined systems. Because of its size, ease of use, and reconfigurability, FPGA represents an attractive alternative in digital design. It is particularly suitable for experimental and rapid prototyping environments.

Different types of FPGA from different vendors are available. The one we will be using is the Xilinx FPGA. Therefore, throughout this document, the term FPGA is referring to the Xilinx FPGA.

In general, there are two kinds of blocks in a Xilinx FPGA: Configurable Logic Blocks (CLB) and Input/Output Blocks (IOB).

Each CLB is capable of supporting generic combinational logic functions of up to 9 inputs and 2 outputs. This is done by using lookup tables. In addition, two flip-flops are provided in each CLB for storing the outputs of the combinational logic, if so desired. Each FPGA contains a good number of CLBs arranged in a 2-dimensional square array to implement and interconnect the desired logic functions of the system. For example, in XC4003, there are 100 CLBs arranged in a 10 by 10 array.

IOBs are used to support the interface, including TTL voltage level, higher driving current, 3-state buffers, etc..., to the external environments. In addition, one flip-flop is also available in each IOB to provide latched input/output. Depending on the size of the chip, different size of FPGA contains different number of IOBs placed on the perimeter of the CLB array. In the case of XC4003, there are 80 IOBs available for external connections.

Configurable routing wires are presented between CLBs and between CLBs and IOBs for interconnecting blocks. The routing wires are arranged in the form of a configurable matrix called switching matrix such that connections from any direction to any other directions are possible.

The Xilinx FPGA design process consists of the following procedures:

2.1  FPGA Design Flow

• Use CAD software to design the circuit schematics.
• Translate the circuit schematics into Xilinx readable format.
• Process the circuit so that it can be mapped into the designated Xilinx part. This process is generally referred to as PPR - Partition, place, and Route.
• Generate the binary image file of the circuit from the result of PPR. This process is called makebits.
• Download the binary image to the FPGA chip.

3  Experimental Procedures

This experiment is to acquaint you with the design process of Xilinx FPGA. You will design a simple circuit for FPGA, download it to FPGA, and verify that it works in hardware.

The CAD tool for drawing the circuit schematics is the Design Architect from Mentor Graphics. The following section will provide a short summary of how to enter a Xilinx FPGAS specific circuit using Mentor Design Architect.

The FPGA chip you will be using is XC4003. It contains 100 CLBs arranged in a 10 by 10 array. In addition, there are 80 IOBs available for external connection. For other properties of XC4003, please consult ``The Programmable Logic Data Book" from Xilinx.

A design example called cnt3 is provided in section  for your reference.

Decide what digital circuit you want to make in an FPGA and draw it in your notebook. Since the purpose of the experiment is to teach you of the flexibility of FPGAs, you need not choose a complex circuit. In fact, we would prefer each pair of students to choose a circuit which is slightly different from that of other students. As a rough measure of size, we suggest something with 3 or 4 flipflops; perhaps a counter, with 1 or 2 gates giving output pulses at particular counts. It is important to have 2 or 3 outputs with easily recognised signals which you can check on an oscilloscope.

As you make up the design, put a truth table or timing diagram (as appropriate for your circuit) into your notebook. This allows you to check the logic of your design as you do it, and later gives you something to check the measured output against.

Later, print out the ECAD schematic and insert it and sketch the waveforms which you observe.

4  Equipment

• A small blue circuit board made by Xilinx with a Xilinx4003pc84-6 FPGA. The board has an RS232 cable to be connected to a workstation.

• A Unix HP Workstation with the Xilinx development software.

• Stabilized voltage supply of +5.0 volts.

• A function Generator from the 623 lab.

• An oscilloscope from the 623 lab.

5  Mentor Design Process

It is assumed that you already know how to draw and edit a schematic using Design Architect software. This section provides a short summary of the Mentor editing notes just for using the Xilinx FPGA.

5.1  Xilinx Design Specific Notes for Mentor Users

• Log on to the HP workstation with your assigned username and password.
• Use the given directory for your username.

  If your username is ``a'' then all your files (such as one called, say, filename) will then have the long pathname:
  /users/a/filename
  or the short pathname:
  ~/a/filename
  For example, the example circuit ``cnt3'' described later has the short pathname
  ~/a/cnt3

• To start mentor's ``Design Architect'' which is called ``da'', type pld_da at the Unix prompt. This executes a script which loads the Xilinx-specific design libraries, namely, XACT_LIB so that you can use the components for Xilinx FPGA. We use this method rather than the method you used in the Mentor lab in order to minimize the effort of starting the Xilinx development system.

• Expand the da window to the full screen by placing the cursor on a corner and ``dragging'' the corner.
• open a new sheet by choosing ``open'' from the ``FILE'' menu. Name the new sheet;
  /users/username/design-name
  where you choose the design-name of your schematic and username is your User Name or, more simply
  ~/username/design-name
  
• There are a few constraints on names used for naming schematics, nets, etc...
  1. The characters that form the name must be from the set of legal characters: {'a'..'z', 'A'..'Z', '0'..'9', '_'}. The characters { '(', ':', ')' } are used to indicate bus width, e.g. Dout(3:0). Note that the schematic file name MAY NOT contain '.' (period).

  2. Do not use capital letters in schematic file names. This is an undocumented bug in Xilinx software.

• Use only the components from XACT_LIB. DO NOT use components from other libraries like gen_lib. Xilinx software doesn't understand anything from libraries other than XACT_LIB. To activate XACT_LIB:
  1. Make sure the schematic window is active by clicking upon it.
  2. select Libraries from the pull-down menu:
     Libraries > XACT_LIB

  3. select UNIFIED LIB from the side pallet.

  4. select XC4000 from the side pallet.
     

            XC4000_LIB > BY TYPE  > arithmetic > ...
                                  > buffer     > ...
                                  > ...        > ...
                    

  5. You will need items from 4 libraries selected from the menu on the right hand side. The 4 are;
     general (for the pullup resistor and the Startup Circuit)
     flip_flop
     logic
     io.

  Please consult the Xilinx Library Reference Manual for the properties of the components and how they behave.

• For external connections, each input must contain a ipad-ibuf block pair, and each output must contain a opad-obuf block pair from the ``io'' library. Please refer to the sample circuit in section .

• Use the command
  SAVE,SHEET every 5 minutes or so so that the file of your sheet is saved to disk and you can recover dfrom a system or operator crash. (You will get a message each save about ``Sheet not checked'', but you can ignore that for now.)
• For the design to be downloadable, it must contain a startup block. Please refer to the sample circuit in section  for exact connections to the startup block.

• DO NOT use Unix cp/mv commands to copy/rename the schematics. Always use the MGC design management tools to copy or rename the design. You can do this in any Mentor application (such as ``Design Architect'') through the MGC menu ``Design Management'' item.

6  Circuit Design Constraints

In reality, all input/output signals are bonded to IC pins. Normally, It is the designer's job to designate the IC pin for each signal. This is referred to as the pinout constraint. In the case of Xilinx FPGA, there are two ways to assign the signals to the IC pins:

1. Leave the pin name unspecified and let the Xilinx software assign the signals to pins automatically. The advantage of this approach is that the designer do not have to worry about the pin assignments, therefore, some labor can be saved. However, there is no guarantee that the next time you run the Xilinx software, you will obtain exactly the same pinout assignment. The software is free to assign any signal to any pin if there is no constraint. This could be annoying if the FPGA is already wired to a system and some design errors are discovered which would require rerunning the layout software.

2. (STRONGLY RECOMMENDED) Specify the pinout by altering (editing) the ``PXX'' designation in the ``opad'' symbol to be ``Pnn'', where nn is the desired pin number. The easiest way to edit this (and the net name outside the symbol) is to

   • place the cursor on the ``PXX'' label WITHOUT CLICKING, then
   • press the shift and F7 keys together then
   • delete the PXX in the tiny window at the bottom of the screen
   • type the desired pin name ``Pnn'' in the tiny window and
   • tap enter to finish.

   This fixes the pinout such that no rewiring is necessary if the design has to undergo several revisions and if you want to use any of the circuit board components such as the LEDs and pushbuttons.

It is suggested that you use the following pins.

P35 for clock.

P56 for active low reset.

P67 through P72 for input signals.

P57 through P62 and P65-66 for output signals since these pins are connected to the LEDs.

The pins which are attached to LED displays on the test board will not interfere with the signals on the pins.)

Use ``Check Sheet'' with default settings then use ``Save Sheet''.

7  Printing Schematics

8  Processing Xilinx Circuits

After the circuit is designed and the pinout properly constrained, you may start mapping the circuit into the Xilinx hardware.

1. The first step in the process is to translate the circuit into Xilinx understandable format, known as the Xilinx Netlist Format, or XNF. All Xilinx software use the XNF format for internal processing.

2. After the circuit is translated into XNF, it is then analyzed for obvious errors. This process is know as the preprocessing step, or prep step. If no error is found, the software then performs logic minimization as much as it can for the circuit.

3. The circuit is then partitioned into small logic blocks such that each block is realizable by a CLB. The placer software will find the locations to place these logic blocks.

4. Finally, the router will interconnect these logic blocks to complete the mapping of the logic functions into FPGA structures.

These four steps are dependent on each other, since optimizing the circuit requires knowledge from each step. Many iterations are required to achieve an optimized solution. Hence, these steps are the most time consuming part in the entire process. Together these steps are called the PPR steps.

After the mapping is done, the makebits software will take the generated mapping and produce a corresponding binary configuration bit file downloadable to the actual FPGA hardware.

8.1  Design Process

Xilinx provides a set of software to perform the above tasks. The procedure using this software is as follows:

1. Change to your directory (for person ``a'') with the command
   cd /users/a.

2. type:
   men2xnf8 design_name -p parttype -verbose
   This software converts the circuit from Mentor representation into XNF format. Parttype is the intended FPGA hardware part. In this experiment, it is 4003pc84-6. 4003 is the Xilinx FPGA part number; pc is the package type; 84 is the number of pins; and -6 is the speed grade of the chip, i.e. 6 ns delay per CLB.

3. xmake -x design_name -g
   Xmake will take you from XNF format all the way to the binary configurable bit file. The option -x means that the circuit representation is in XNF format. The option -g means to stop processing after generating the design_name.mak file. The design_name.mak file is a text file that contains all the processing commands necessary to take you from the XNF to the bit file. Xmake follows these commands to generate the bit file. The reason for stopping at this point is because you need to set some options in one of the commands, namely, makebits, to adjust it to the hardware environment in the lab, as described in to the following step.

4. Edit the design_name.mak file:
   Edit the line containing makebits such that it look like the following:
   

       makebits -f DonePin:Pullup design_name.lca
           

   Edit by clicking the small ``pencil and paper'' icon on the bottom bar or use the Unix editors ``vi'' or ``emacs'' if you prefer.

   The option -f DonePin:Pullup ties a pullup resistor to one of the download configuration pins, namely the DonePin. This step is necessary since this open drain pin is used to indicate when the bit file download is complete. Without the pullup resistor, the open drain pin will never go high to indicate the completion of the process.

5. xmake design_name.mak
   The design_name.mak command file is now ready. This step uses the design_name.mak file as a command file to complete the Xilinx FPGA design process.

1. men2xnf8 cnt3 -p 4003pc84-6 -verbose
2. xmake -x cnt3 -g
   
3. Edit the cnt3.mak file:
   Edit line: makebits -f DonePin:Pullup cnt3.lca
4. xmake cnt3.mak. This command creates the ``cnt3.bit'' file which will be downloaded to the Xilinx chip.
   

8.2  Error Checking and the Report File

If errors occur in any of the design procedure, error messages will be written to one of the report files. For preprocessing errors, please check design_name.prp file; for PPR errors, please check design_name.out file. If there are errors, go back to the Mentor circuit editing process to correct the errors and follow the entire design process again.

If there is no error, the design_name.rpt file will report the result of the mapping process. The resource usage including CLB and IOB will be reported as well as the worst case delay. In addition, the pinout assignment will be generated, or confirmed if the pinout constraint is used. Please check the pinout assignment in this report file to verify the validity of the assignment.

If you wish, you can print out a copy of this file with the Unix print command;
lp -d printername design-name.rpt and include it in your notebook.

9  Xchecker Downloading

The binary configuration bit file is now ready to be downloaded to the actual FPGA chip. Please follow the following steps for downloading.

1. Make sure the FPGA chip and the external environment such as Vcc (=+5.00 volt), ground, and clock are wired properly.

2. Power on the Vcc, and Vcc only! Do not power on the clock yet. (Beware, the signal generator ``disable'' button turns off the clock when the light is on.

3. Type xchecker
   

   Xchecker is the Xilinx interface between software and the actual FPGA hardware.

4. Type load design_name.bit at the xchecker prompt; ``XCHECKER?''. Press return if necessary to start downloading.

5. After receiving the message "DONE signal went high," you may exit the xchecker environment by typing quit.

The following is the transcript of the xchecker commands for downloading the cnt3 sample circuit.

matatua 37: xchecker
Xilinx (R) XCHECKER 5.0.0 - Download/Readback LCA via download cable
Copyright (C) Xilinx Inc. 1991-1994. All Rights Reserved.
--------------------------------------------------------------------
Cable ID type is 'SERIAL-READBACK'
Cable is connected to '/dev/tty00'
Baud rate is 38400
XCHECKER ? load cnt3.bit

About to download 'cnt3.bit'.
Press ENTER key to continue or Q to quit:
> 
Total of 6747 bytes transmitted.
DONE signal went high.
Transmitting time =  3.34 secs
XCHECKER ? quit
Profile is saved in xchecker.pro
matatua 38: 

The binary configuration bit file is now successfully downloaded to the FPGA. You may now enable the clock signal. Press the RESET button if necessary.

10  Verifying that the Circuit is Running

Use the oscilloscope to look at the clock signal and the outputs from your circuit. The layout of the FPGA pin locations is given on the last page of this experiment description.

11  Sample Circuit

A sample circuit cnt3 is provided in this section for reference. It is a binary 3 bit synchronous up counter. The circuit diagram is provided. Please refer to it as you construct your experimental circuit.

11.1  Circuit Diagram

Figure 1: